1. Field of the Invention
This invention relates to top collector contacted transistors, and more particularly, to the design of a distributed collector ballast resistor structure.
2. Prior Art
A main objective in the design of transistors is enhanced uniformity of power dissipation under collector-base junction reverse bias avalanche conditions.
Presently, the most effective method of limiting the current due to avalanche is to employ an epitaxial layer thickness greater than that required to support the depletion width. This thickness serves as a single bulk resistor in series with the collector circuit. One of the problems with this method is that a compromise must be struck between allowing low saturation voltage during normal operation and effecting lower current for a given voltage during avalanche.
It is therefore an object of this invention to provide a collector ballast resistor structure whereby a lower current is effected for a given voltage during avalanche while during normal operation allowing lower saturated voltage V.sub.CE(SAT), better RF gain and higher saturated output power relative to prior art designs.